A typical CMOS circuit application can provide very low standby power. Current flows in the circuit only when a transition of state is occurring. This feature makes it extremely easy to manage the power dissipation in CMOS designs. For an n-channel MOS device the current carriers are electrons, whereas for a p-channel MOS device the carriers are holes. Four separate regions or terminals exist in a MOS transistor: source, drain, gate, and substrate. For normal operation, the source, drain, and gate voltages measured with respect to substrate are positive for an n-channel device and negative for a p-channel device. The output is always connected to one of the power supply rails because at any given state only one transistor is on and the other is off. This guarantees that the logic swing will be determined by the power supply voltage only, and not by the ratio of the effective impedance of the devices, as is the case with static nMOS design.
In semiconductor technology, polycrystalline silicon (polysilicon) is very frequently used as a gate electrode. The popularity of polysilicon is largely due to the fact that polysilicon is a particularly suitable material in self-registering MOS processes, in which the gate electrode and source/drain areas are defined by the same masking step. In integrated circuits, polysilicon is used for circuit wiring as well as a gate electrode.
In the realization of submicron MOSFETs decreasing gate oxide thickness (T.sub.OX), the correspondingly increasing electric field across the thin dielectric is a major concern. With gate oxide thickness of 10 nm and smaller, the supply voltage had to be reduced from 5 V to 3.3 V in order to reduce the electric field across the dielectric to a safe level of below 4 MV/cm. However, with decreasing supply voltage, the field enhancement caused by the workfunction difference between the n.sup.+ gates and p.sup.+ junctions, or the p.sup.+ gates and n.sup.+ junctions, becomes increasingly important. The workfunction difference of 1.1 eV remains constant with decreasing supply voltage. The oxide field (E.sub.OX) can be calculated by utilizing the formula shown in Equation 1 where V.sub.gate represents the gate voltage, V.sub.fb represents the flatband voltage, and T.sub.OX represents the oxide thickness. EQU E.sub.OX =[(.+-.V.sub.gate)+(.+-.V.sub.fb)]/T.sub.OX
Equation 1.
The flatband voltage (V.sub.fb) can be calculated by utilizing the formula shown in Equation 2 where .phi..sub.ms represents the workfunction difference, Q.sub.ox represents the oxide charge and C.sub.ox the oxide capacitance. EQU V.sub.fb =.phi..sub.ms +Q.sub.ox /C.sub.ox
Equation 2.
Depending upon the bias of the gate and source, the workfunction difference (.phi..sub.ms) will increase or decrease the electric field in the gate/junction region as evident from Equation 1. FIG. 1 illustrates the gate-to-junction area of a MOSFET 10, having an n.sup.+ gate 12, n.sup.- substrate 14 and p.sup.+ junction 16 with a gate oxide thickness (T.sub.OX) 18. The oxide field 20 is affected by the workfunction difference (.phi..sub.ms) according to Equation 1.
Referring to FIG. 2, there is shown, the effect of the gate polarity on oxide field between source and drain of n.sup.+ PMOS devices and p.sup.+ PMOS devices which are in a conducting state, turned on. FIG. 3. shows the simulated oxide field along the channel for n.sup.+ PMOS and p.sup.+ PMOS devices which are in a non-conducting state, turned off. The field enhancement of approximately 1 MV/cm for n.sup.+ PMOS FETs is due to the added workfunction difference. The results shown in FIGS. 2 and 3 were obtained with two dimensional computer simulations utilizing MINIMOS. In the non-conducting off state the oxide field is increased by the workfunction difference up to 4.6 MV/cm at the drain side for the n.sup.+ gate PMOS when a nominal oxide thickness of 10 nm is assumed. When a process variation of 10% in T.sub.OX is accounted for, a maximum oxide field of 5 MV/cm will result. This enhanced oxide field will increase the risk of device failures such as oxide breakdowns and device instabilities.
MOSFETs having equal gate and junction dopant type, i.e. p.sup.+ gate PMOS and n.sup.+ gate NMOS, have been proposed in order to avoid the high oxide fields which were described above. Referring to FIGS. 2 and 3, it can be seen that the oxide field of the p.sup.+ gate PMOS device remains below 3.6 MV/cm. However, the actual implementation of such a symmetrical device design in CMOS technology complicates the process substantially. This is because a dual workfunction gate technology is required. Information on the feasibility of fabricating dual gate CMOS devices can be obtained by referring to an article entitled "Doping of n+ and p+ Polysilicon in a Dual-Gate CMOS Process" by C. Y. Wong et al published by IEEE in IEDM Tech. Dig. 238 (1988). A polysilicon depletion occurs at reverse biases, which causes device current degradation. This effect becomes more severe as the gate oxide thickness (T.sub.OX) becomes smaller. Reference is made to an article entitled "Effects of Depleted Poly-Si Gate on MOSFET Performance" by M. Iwase et al published in Ext. Abstract SSDM 271 (1990) for information on dual gate symmetric CMOS structures for sub-micron integration and degradation of performance by the depleted gate on the device.
Therefore, reducing the workfunction related high oxide fields for single workfunction gate technologies, such as for n.sup.+ gate only and p.sup.+ gate only, for CMOS is highly desirable. One solution is through the controlled formation of gate birds beaks which have the tendency to increase the oxide thickness at the gate edges. This solution, however leads to a transconductance degradation which results in a loss of performance.
It is an object of the present invention to reduce the oxide field over the junction area.